Clock signals are used in virtually every IC and electronic system to control timing. For example, every time there is a rising edge on a clock signal, all the latches in a circuit may change state. Many DSP (digital signal processor) tools employ DSP evaluation boards to evaluate DSPs. These DSP evaluation boards are often debugged using an emulator, which are also referred to as in-circuit emulator (ICE). The emulators are hardware tools that are generally used for software development, including testing in real-time. They also facilitate in modifying and displaying data stored in memories and registers, which can help verify the operation of a system hardware and software. With advances in high-speed DSPs that can handle complicated and larger application, higher seed emulators can significantly reduce application development time.
However, the communication speed between the emulator and the evaluation board is limited by the delay introduced in the digital circuit included between them. Thus, to improve the communication speed and the performance between the evaluation board and the emulator, the delay introduced in the digital circuit has to be compensated and/or reduced.
One conventional technique compensates such delay between the emulator and the evaluation board using a bit error test (i.e., by raising the clock frequency until communication from the evaluation board fails, and then selecting a slightly lower frequency). This technique does not adjust the skew to synchronize the sample clock with delayed returning data rather it simply finds the failure point in the system by decreasing the sampling period (i.e., by increasing the frequency). This can lead to a less than desired operating frequency.
Another conventional technique uses a user-specified clock from the evaluation board to clock data back to the emulator. This clock automatically includes/accounts for the timing delays introduced by the evaluation board. This approach requires adding another pin to the evaluation board.